PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Figure 18
- STM-1 Input Bus Timing - Simple STS-1/AU3 Case
SCLK
IC1J1[n]
••••
IPL[n]
ITMF[n]
(ITMFH4=1)
ID[7:0] (n=1)
ID[15:8] (n=2)
ID[23:16] (n=3)
ID[31:24] (n=4)
A1 A1 A1 A2 A2 A2 C1 C1 C1 J1 J1 J1
STS-1 #1 SPE J1 byte
H2 H3 H3 H3
H4 H4 H4
No stuffing
occuring
STS-1 #2 SPE J1 byte
STS-1 #3 SPE J1 byte
Figure 19 shows a more complex STS-3 case that illustrates the flexibility
provided by the various input signals associated with each of the four input buses
when the TUPP+622 is in STM-1 (STS-3) input interface mode (IHSMODEB set
high) (n is {1, 2, 3, 4}). Data on ID[7:0] (ID[15:8], ID[23:16], ID[31:24]) is sampled
on the rising edge of SCLK. The bytes forming the three STS-1 synchronous
payload envelopes are identified by the IPL[1] (IPL[2], IPL[3], IPL[4]) signal being
set high. This example shows a negative stuff event occurring on STS-1 #2 and a
positive stuff event occurring on STS-1 #3. The IC1J1[1] (IC1J1[2], IC1J1[3],
IC1J1[4]) signal pulses high while IPL[1] (IPL[2], IPL[3], IPL[4]) is low to mark the
position of the C1 byte of STS-1 #1. The IC1J1[1] (IC1J1[2], IC1J1[3], IC1J1[4])
signal pulses high again to mark the J1 byte of each of the three STS-1 SPEs.
The ITMF[1] (ITMF[2], ITMF[3], ITMF[4]) signal is selectable to mark the third
byte after J1 in an STS-1 SPE or the H4 byte in the last (fourth) frame of a
tributary multiframe. In this diagram, ITMF[1] (ITMF[2], ITMF[3], ITMF[4]) is
shown to be marking the V1 byte of the first tributary multiframe in STS-1 #2. The
three STS-1 SPEs are shown to have different alignments to the STS-3 transport
envelope and the alignment is changing for two of the STS-1 SPEs (STS-1 #1
and #2) due to the pointer justification events shown. Other alignments are
possible. The four input buses can be independently configured to handle STS-
1/AU3 or AU4 and the SPE/VC alignments of the input buses may be different.
However, the transport frame alignments of the four input buses must be
identical. That is, the C1 portion of all the IC1J1[4:1] signals must be coincident.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
390
PMC [ PMC-SIERRA, INC ]
