PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Pin Name
HSCLK
Type
Pin
Function
No.
Input
K4
The High-Speed STM-4 (STS-12) interface
mode system clock (HSCLK) provides timing for
TUPP+622 internal operations in incoming or
outgoing STM-4 (STS-12) interface mode
(IHSMODEB or OHSMODEB set low). HSCLK is
a 77.76 MHz, nominally 50% duty cycle, clock.
In incoming STM-4 (STS-12) interface mode
(IHSMODEB set low), IC1J1[1], IPL[1], ITMF[1],
IDP[1], ID[7:0], ITV5[1], ITPL[1] and IAIS[1] are
sampled on the rising edge of HSCLK. In
outgoing STM-4 (STS-12) interface mode
(OHSMODEB set low), OTMF[1] and
GSCLK_FP are sampled on the rising edge of
HSCLK, and ODP[1], OTPL[1], OTV5[1],
OD[7:0], AIS[1], IDLE[1], TPOH[1], OC1J1V1[1]
and OPL[1] are updated on the rising edge of
HSCLK. When the incoming and the outgoing
interfaces are in STM-1 mode (IHSMODEB and
OHSMODEB both set high), HSCLK may be left
unconnected. HSCLK has an integral pull-up
resistor.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
18
PMC [ PMC-SIERRA, INC ]
