PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Pin Name
Type
Pin
No.
Function
GSCLK[1]
GSCLK[0]
Output N4
N3
The generated system clock (GSCLK[1:0])
signals provide timing for the TUPP+622 when
STM-4 (STS-12) interface mode is selected at
the incoming or outgoing interface (IHSMODEB
or OHSMODEB set low). GSCLK[1:0] are a
divide by four of HSCLK. GSCLK[0] must only
be connected to SCLK externally when
IHSMODEB or OHSMODEB is set low.
GSCLK[1] is a exact replica of GSCLK[0] and
can be used to supply timing to external devices
that are operating in the 19.44 MHz STM-1
(STS-3) interface timing domain. GSCLK[1:0]
are updated on the rising edge of HSCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
20
PMC [ PMC-SIERRA, INC ]
