PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
9
PIN DESCRIPTION (304)
Pin Name
Type
Pin
No.
Function
SCLK/
Input
P1
The system clock (SCLK) provides timing for
TUPP+622 internal operations. SCLK is a
19.44 MHz, nominally 50% duty cycle, clock.
When either incoming interface is in STM-4
mode (IHSMODEB set low) or the outgoing
interface is in STM-4 mode (OHSMODEB set
low), SCLK must be connected to GSCLK[0]
externally.
In incoming STM-1 (STS-3) interface mode
(IHSMODEB set high), IC1J1[4:1], IPL[4:1],
ITMF[4:1], IDP[4:1], ID[31:0], ITV5[4:1],
ITPL[4:1], IAIS[4:1] and OTMF[4:1] are sampled
on the rising edge of SCLK. In outgoing STM-1
(STS-3) interface mode (OHSMODEB set high),
ODP[4:1], OTPL[4:1], OTV5[4:1], OD[31:0],
AIS[4:1], IDLE[4:1], TPOH[4:1], OC1J1V1[4:1]
and OPL[4:1] are updated on the rising edge of
SCLK.
VCLK
The test vector clock (VCLK) signal is used
during TUPP+622 production testing to verify
manufacture.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
17
PMC [ PMC-SIERRA, INC ]
