PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
generated when the accepted PSL becomes matched to the expected PSL or
becomes mismatched to the expected PSL. An PSLMxI bit is set high when a
change of PSL matched state on the associated tributary (TU #1 in TUG2 #x)
occurs and are cleared immediately following a read of this register, which
also acknowledges and clears the interrupt. PSLMxI remains valid when
interrupts are not enabled (PSLME set low) and may be polled to detect path
signal label match/mismatch events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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