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PM5363-BI 参数 Datasheet PDF下载

PM5363-BI图片预览
型号: PM5363-BI
PDF下载: 下载PDF文件 查看货源
内容描述: SONET / SDH支路单元荷载处理器, 622兆比特/ s接口 [SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 459 页 / 3435 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM5363 TUPP+622  
TUPP+622  
DATASHEET  
PMC-1981421  
ISSUE 4  
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S  
INTERFACES  
multiframe. When ITMFH4 is set low, ITMF marks the third byte after J1.  
ITMFH4 is ignored if ITMF is disabled by setting the ITMFEN bit low.  
IOP:  
The IOP bit controls the expected parity on the corresponding incoming parity  
signal IDP. When IOP is set high, the parity of the parity signal set, together  
with IDP is expected to be odd. When IOP is set low, the expected parity is  
even. Membership of the parity signal set always includes ID[7:0], and may  
include input signals IC1J1 and IPL as controlled by the INCIC1J1 and  
INCIPL bits, respectively.  
INCIC1J1:  
The INCIC1J1 bit controls whether the corresponding IC1J1 input signal  
participates in the incoming parity calculations. When INCIC1J1 is set high,  
the parity signal set includes the IC1J1 input. When INCIC1J1 is set low,  
parity is calculated without regard to the state of IC1J1. Selection of odd or  
even parity is controlled by the IOP bit.  
INCIPL:  
The INCIPL bit controls whether the corresponding IPL input signal  
participates in the incoming parity calculations. When INCIPL is set high, the  
parity signal set includes the IPL input. When INCIPL is set low, parity is  
calculated without regard to the state of IPL. Selection of odd or even parity is  
controlled by the IOP bit.  
LOPAIS:  
The LOPAIS bit is an active high AIS insertion enable. When LOPAIS is set  
high, AIS is automatically generated on the corresponding outgoing data  
stream for all tributaries that are in loss of pointer state. When LOPAIS is set  
low, the generation of AIS on the outgoing data stream is inhibited. This bit is  
logically OR'ed with the bit of the same name in Tributary Alarm AIS Control  
register.  
IPE:  
The IPE bit is an active high interrupt enable. When IPE is set high, the  
occurrence of a parity error on the corresponding incoming parity signal set  
will cause an interrupt to be asserted on the interrupt (INTB) output. When  
IPE is set low, incoming parity errors will not cause an interrupt.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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