PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
11
NORMAL MODE REGISTER DESCRIPTION
Normal mode registers are used to configure and monitor the operation of the
TUPP+622. Normal mode registers (as opposed to test mode registers) are
selected when TRS (A[13]) is low.
Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
unused register bits must be written with logic 0. Reading back unused bits
can produce either a logic 1 or a logic 0; hence unused register bits should be
masked off by software when read.
2. All configuration bits that can be written into can also be read back. This
allows the processor controlling the TUPP+622 to determine the programming
state of the device.
3. Writeable normal mode register bits are cleared to logic 0 upon reset unless
otherwise noted.
4. Writing into read-only normal mode register bit locations does not affect
TUPP+622 operation unless otherwise noted.
5. Certain register bits are reserved. These bits are associated with megacell
functions that are unused in this application. To ensure that the TUPP+622
operates as intended, reserved register bits must only be written with the logic
level as specified. Writing to reserved registers should be avoided.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
117
PMC [ PMC-SIERRA, INC ]
