PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 02H: STP Input Signal Activity Monitor #1, Accumulation Trigger
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
OTMFA
Unused
GSCLK_FPA
IDA
X
X
X
X
X
X
X
X
R
R
R
R
R
R
ITMFA
IPLA
IC1J1A
SCLKA
This register, along with the STP Input Signal Activity Monitor #2, provides activity
monitoring on major TUPP+622 inputs. When a monitored input makes a low to
high transition, the corresponding register bit is set high. The bit will remain high
until this register is read, at which point, all the bits in this register are cleared. A
lack of transitions is indicated by the corresponding register bit reading low. This
register should be read periodically to detect for stuck at conditions.
Writing to this register delimits the accumulation intervals in the RTOP
accumulation registers. Counts accumulated in those registers are transferred to
holding registers where they can be read. The counters themselves are then
cleared to begin accumulating events for a new accumulation interval. To prevent
loss of data, accumulation intervals must be 0.5 second or shorter. The bits in
this register are not affected by write accesses.
SCLKA:
The SCLK active (SCLKA) bit monitors for low to high transitions on the SCLK
input. SCLKA is set high on a rising edge of SCLK, and is set low when this
register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
122
PMC [ PMC-SIERRA, INC ]
