PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
10 FUNCTIONAL DESCRIPTION
10.1 Receive Line Interface (CRSI-622)
The Receive Line Interface allows direct interface of the S/UNI-622-MAX to optical modules
(ODLs) or other medium interfaces. This block performs clock and data recovery on the incoming
622.08 Mbit/s data stream and SONET/SDH A1/A2 pattern framing.
Clock Recovery
The clock recovery unit recovers the clock from the incoming bit serial data stream and is
compliant with SONET and SDH jitter tolerance requirements. The clock recovery unit utilizes a
low frequency reference clock to train and monitor its clock recovery PLL. Under loss of transition
conditions, the clock recovery unit continues to output a line rate clock that is locked to this
reference for keep alive purposes. The clock recovery unit utilizes a 77.76 MHz reference clock.
The clock recovery unit provides status bits that indicate whether it is locked to data or the
reference and also supports diagnostic loopback and a loss of signal input that squelches normal
input data.
Initially upon start-up, the PLL locks to the reference clock, REFCLK. When the frequency of the
recovered clock is within 488 ppm of the reference clock, the PLL attempts to lock to the data.
Once in data lock, the PLL reverts to the reference clock if no data transitions occur in 96 bit
periods or if the recovered clock drifts beyond 488 ppm of the reference clock.
When the transmit clock is derived from the recovered clock (loop timing), the accuracy of the
transmit clock is directly related to the REFCLK reference accuracy in the case of a loss of
transition condition. To meet the Bellcore GR-253-CORE SONET Network Element free-run
accuracy specification, the reference must be within +/-20 ppm. For LAN applications, the
REFCLK accuracy may be relaxed to +/-50 ppm.
The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the
minimum transition density expected in a received SONET/SDH data signal. The total loop
dynamics of the clock recovery PLL yield a jitter tolerance that exceeds the minimum tolerance
specified for SONET/SDH equipment by GR-253-CORE.
Note that for frequencies below 300Hz, the jitter tolerance is greater than 22 UIpp; 22UIpp is the
maximum jitter tolerance of the test equipment. The dip in the jitter tolerance curve between 10
kHz and 30 kHz is due to the clock difference detector.
The typical jitter tolerance performance of the S/UNI-622-MAX is shown in Figure 3 with the GR-
253-CORE jitter tolerance specification limits. The jitter tolerance setup used a Hewlett Packard
HFBR-5208M multi-mode fiber optic transceiver with approximately -10 dBm input power. The
RTYPE register bit in CRSI-622 was set to logic zero.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
40
PMC [ PMC-SIERRA, INC ]
