PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. The LAIS signal
is optionally reported on the RALRM output pin when enabled by the LAISEN Receive Alarm
Control Register bit.
Error Monitor Block
The Error Monitor Block calculates the received line BIP-8 error detection codes based on the
Line Overhead bytes and synchronous payload envelopes of the STS-12c/STM-4-4c stream.
The line BIP-8 code is a bit interleaved parity calculation using even parity. Details are provided
in the references. The calculated BIP-8 codes are compared with the BIP-8 codes extracted from
the following frame. Any differences indicate that a line layer bit error has occurred. Optionally
the RLOP can be configured to count a maximum of only one BIP error per frame.
This block also extracts the line FEBE code from the M1 byte. The FEBE code is contained in
bits 2 to 8 of the M1 byte, and represents the number of line BIP-8 errors that were detected in
the last frame by the far end. The FEBE code value has 97 legal values (0 to 96) for an STS-
12c/STM-4-4c stream. Illegal values are interpreted a zero errors.
The Error Monitor Block accumulates B2 error events and FEBE events in two 20-bit saturating
counters that can be read via the CBI. The contents of these counters may be transferred to
internal holding registers by writing to any one of the counter addresses, or by using the TIP
register bit feature. During a transfer, the counter value is latched and the counter is reset to 0 (or
1, if there is an outstanding event). Note, these counters should be polled at least once per
second to avoid saturation.
The B2 error event counters optionally can be configured to accumulate only "word" errors. A B2
word error is defined as the occurrence of one or more B2 bit error events during a frame. The
B2 error counter is incremented by one for each frame in which a B2 word error occurs.
In addition the FEBE events counters optionally can be configured to accumulate only "word"
events. A FEBE word event is defined as the occurrence of one or more FEBE bit events during
a frame. The FEBE event counter is incremented by one for each frame in which a FEBE event
occurs. If the extracted FEBE value is in the range 1 to 4 the FEBE event counter will be
incremented for each and every FEBE bit. If the extracted FEBE value is greater then 4 the
FEBE event counter will be incremented by 4.
10.4 The Receive APS, Synchronization Extractor and Bit Error Monitor (RASE)
Automatic Protection Switch Control
The Automatic Protection Switch (APS) control block filters and captures the receive automatic
protection switch channel bytes (K1 and K2) allowing them to be read via the RASE APS K1
Register and the RASE APS K2 Register. The bytes are filtered for three frames before being
written to these registers. A protection switching byte failure alarm is declared when twelve
successive frames have been received, where no three consecutive frames contain identical K1
bytes. The protection switching byte failure alarm is removed upon detection of three consecutive
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
44
PMC [ PMC-SIERRA, INC ]
