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PM5356-BI 参数 Datasheet PDF下载

PM5356-BI图片预览
型号: PM5356-BI
PDF下载: 下载PDF文件 查看货源
内容描述: [ATM Network Interface, 1-Func, CMOS, PBGA304, SBGA-304]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 278 页 / 1562 K
品牌: PMC [ PMC-SIERRA, INC ]
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PMC-Sierra, Inc.  
PM5356  
S/UNI-622-MAX  
DATASHEET  
S/UNI-622-MAX  
PMC-1980589  
ISSUE 5  
SATURN USER NETWORK INTERFACE (622-MAX)  
Notes on Pin Description:  
1. All S/UNI-622-MAX inputs and bi-directional signals present minimum capacitive loading and  
operate at TTL logic levels except the inputs marked as Analog or differential pseudo-ECL  
(PECL).  
2. The RDAT[15:0], RCA, RCLK, RFPO, RVAL, TCA, TCLK, TFPO, POUT[7:0], FPOUT and  
OOF outputs have a 8mA drive capability. The TDO and INTB outputs have a 2mA drive  
capability. All other digital outputs and bi-directional signals have 4mA drive capability.  
3. The system interface inputs RFCLK, RENB, TFCLK, TENB, TDAT[15:0], and TPRTY do not  
use the ESD bias voltages (VBIAS and PBIAS pins) and are 3.3V tolerate only. All other  
digital inputs (excluding inputs marked Analog), may operate with 5V signalling with  
appropriate ESD biasing.  
4. The differential pseudo-ECL inputs and outputs should be terminated in a passive network  
and interface at PECL levels as described in the Operations section.  
5. It is mandatory that every digital ground pin (VSS) be connected to the printed circuit board  
ground plane to ensure reliable device operation.  
6. It is mandatory that every digital power pin (VDD) be connected to the printed circuit board  
power plane to ensure reliable device operation.  
7. All analog power and ground pins can be sensitive to noise. They must be isolated from the  
digital power and ground. Care must be taken to correctly decouple these pins. Please refer  
to the Operation section and the S/UNI-622-MAX reference design (PMC-981070) for more  
information.  
8. Due to ESD protection structures in the pads it is necessary to exercise caution when  
powering a device up or down. ESD protection devices behave as diodes between power  
supply pins and from I/O pins to power supply pins. Under extreme conditions it is possible  
to damage these ESD protection devices or trigger latch up. Please adhere to the  
recommended power supply sequencing as described in the Operation section of this  
document.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERSINTERNAL USE  
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