Pm49FL002 / 004
PMC
FWH MODE OPERATION
FWH MODE MEMORY READ/WRITE OPERATION
FWH ABORT OPERATION
In FWH mode, the Pm49FL002/004 are connected
through a 5-pin communication interface - FWH[3:0] and
FWH4 pins to work with Intel® Family of I/O Controller
Hubs (ICH) chipset platforms. The FWH mode also sup-
port JEDEC standard Software Data Protection (SDP)
product ID entry, byte program, sector erase, and block
erase command sequences. The chip erase command
sequence is only available in A/A Mux mode.
The FWH4 signal indicates the start of a memory cycle
or the termination of a cycle in FWH mode. Asserting
FWH4 for one or more clock cycle with a valid START
value on FWH[3:0] will initiate a memory read or memory
write cycle. If the FWH4 is driven low again for one or
more clock cycles during this cycle, this cycle will be
terminated and the device will wait for the ABORT com-
mand “1111b” to release the FWH[3:0] bus. If the abort
occurs during the program or erase operation such as
checking the operation status with Data# Polling (I/O7)
or Toggle Bit (I/O6) pins, the read status cycle will be
aborted but the internal program or erase operation will
not be affected. Only the reset operation initiated by RST#
or INIT# pin can terminate the program or erase opera-
tion.
The addresses and data are transmitted through the 4-
bit FWH[3:0] bus synchronized with the input clock on
CLK pin during a FWH memory cycle operation. The
address or data on FWH[3:0] bus is latched on the ris-
ing edge of the clock. The pulse of FWH4 pin inserted
for one clock indicates the start of a FWH memory read
or memory write cycle.
Once the FWH memory cycle is started, asserted by
FWH4, a START value “11xxb” is expected by
Pm49FL002/004 as a valid command cycle and is used
to indicates the type of memory cycle (“1101b” for FWH
memory read cycle or “1110b” for FWH memory write
cycle). Addresses and data are transferred to and from
the device decided by a series of “fields”. Field sequences
and contents are strictly defined for FWH memory read
and write operations. Refer to Table 2 and 3 for FWH
Memory Read Cycle Definition and FWH Memory Write
Cycle Definition.
There are 7 clock fields in a FWH memory cycle that
gives a 28 bit memory address A27 - A0 through
FWH[3:0] pins, but only the last five address fields will
be decoded by the FWH devices. The Pm49FL002 de-
codes A17 - A0 with A19 and A18 ignored. The
Pm49FL004 decodes A18 - A0 with A19 ignored. The
address A22 has the special function of directing reads
and writes to the Flash array when A22 = 1 or to the
register space with A22 = 0. The A27 - A23 and A21 -
A20 are don’t care for the devices under FWH mode.
The Pm49FL002/004 are mapped within the top 4 Mbyte
address range devoted to the FWH devices in the 4 Gbyte
system memory space. Please see Table 11 for System
Memory Map.
Issue Date: December, 2003 Rev: 1.4
Programmable Microelectronics Corp.
9
PMC [ PMC-SIERRA, INC ]
