Pm49FL002 / 004
PMC
FWH MODE OPERATION (CONTINUED)
Table 2: FWH Memory Read Cycle Definition
Clock Cycle
Field
FWH[3:0] Direction Description
Start of Cycle: "1101b" to indicate the start of a memory
read cycle.
1
START
1101
IN
IN
ID Select Cycle: Indicates which FWH device should respond.
If the IDSEL field matches the value set on ID[3:0] pins, then
the particular FWH device will respond to subsequent
commands.
0000 to
1111
2
IDSEL
Address Cycles: This is the 28-bit memory address. The
addresses transfer most-significant nibble first and least-
significant nibble last. (i.e., A27 - 24 on FWH[3:0] first, and
A3 - A0 on FWH[3:0] last).
3-9
10
IMADDR
IMSIZE
YYYY
IN
IN
Memory Size Cycle: Indicates how many bytes will be or
transferred during multi-byte operations. The Pm49FL00x only
support "0000b" for one byte operation.
0000
1111
IN then
Float
Turn-Around Cycle 0: The Intel ICH has driven the bus then
float it to all "1"s and then floats the bus.
11
12
13
TAR0
TAR1
1111
(float)
Float then Turn-Around Cycle 1: The device takes control of the bus
OUT
during this cycle.
0000
(READY)
Ready Sync: The FWH device indicates the least-significant
nibble of data byte will be ready in next clock cycle.
RSYNC
OUT
Data Cycles: The 8-bits data transferred with least-significant
nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on
LAD[3:0] first, then I/O7 - I/O4 on FWH[3:0] last).
14-15
DATA
YYYY
OUT
OUT then Turn -Around Cycle 0: The FWH device has driven the bus
Float then float it to all "1"s and then floats the bus.
Float then Turn-Around Cycle 1: The Intel ICH resumes control of the bus
16
17
TAR0
TAR1
1111
1111
(float)
IN
during this cycle.
FWH MEMORY READ CYCLE WAVEFORMS
CLK
RST# or INIT#
FWH4
Memory
Read
IDSEL
Start
IMSIZE
0000b
RSYNC
0000b
Address
Data
Next Start
1101b
Tri-State
TAR
TAR
xxxxb
A[15:12]
A[11:8]
A[7:4]
1111b
2
Tri-State
1101b
Clock
ID[3:0]
Clock
x1xxb
A[19:16]
A[3:0]
D[3:0]
D[7:4]
1111b
2
FWH[3:0]
1
1
Clocks
1
Clock
Data Out
2
Clocks
1 Clock
Clocks
Load Address in
7 Clocks
From Host to Device
From Device to Host
Issue Date: December, 2003 Rev: 1.4
Programmable Microelectronics Corp.
10
PMC [ PMC-SIERRA, INC ]
