Pm49FL002 / 004
PMC
FWH MODE OPERATION (CONTINUED)
Table 3: FWH Memory Write Cycle Definition
FWH[3:0] Direction Description
Clock Cycle
Field
Start of Cycle: "1110b" to indicate the start of a memory
write cycle.
1
START
1110
IN
ID Select Cycle: Indicates which FWH device should respond.
If the IDSEL field matches the value set on ID[3:0] pins, then
the particular FWH device will respond to subsequent
commands.
0000 to
1111
2
IDSEL
IN
Address Cycles: This is the 28-bit memory address. The
addresses transfer most-significant nibble first and least-
significant nibble last. (i.e., A27 - 24 on FWH[3:0] first, and
A3 - A0 on FWH[3:0] last).
3-9
IMADDR
YYYY
0000
IN
Memory Size Cycle: Indicates how many bytes will be or
transferred during multi-byte operations. The Pm49FL00x only
support "0000b" for one byte operation.
10
IMSIZE
DATA
IN
IN
Data Cycles: The 8-bits data transferred with least-significant
nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on
LAD[3:0] first, then I/O7 - I/O4 on FWH[3:0] last).
11-12
YYYY
1111
IN then
Float
Turn-Around Cycle 0: The Intel ICH has driven the bus then
float it to all "1"s and then floats the bus.
13
14
15
16
17
TAR0
TAR1
1111
(float)
Float then Turn-Around Cycle 1: The device takes control of the bus
OUT
during this cycle.
0000
(READY)
Ready Sync: The FWH device indicates that it has received
the data or command.
RSYNC
TAR0
OUT
OUT then Turn-Around Cycle 0: The FWH device has driven the bus
Float then float it to all "1"s and then floats the bus.
Float then Turn-Around Cycle 1: The Intel ICH resumes control of the bus
1111
1111
(float)
TAR1
IN
during this cycle.
FWH MEMORY WRITE CYCLE WAVEFORMS
CLK
RST# or INIT#
FWH4
Memory
Write
Start
IDSEL
Address
IMSIZE
0000b
Data
TAR
RSYNC
0000b
Next Start
1110b
TAR
xxxxb
x1xxb
A[11:8]
Clocks
A[7:4]
A[3:0]
D[3:0]
D[7:4]
1111b
2
1110b
Clock
ID[3:0]
Clock
A[19:16] A[15:12]
Tri-State
1111b Tri-State
FWH[3:0]
1
1
1
Clock
Clocks
1
Clock
2
Clocks
1 Clock
Load Data in
2 Clocks
Load Address in
7
From Host to Device
From Device to Host
Issue Date: December, 2003 Rev: 1.4
Programmable Microelectronics Corp.
11
PMC [ PMC-SIERRA, INC ]
