Pm49FL002 / 004
PMC
PIN DESCRIPTIONS
Interface
SYMBOL TYPE
DESCRIPTION
PP FWH LPC
Address Inputs: For inputing the multiplex addresses and commands in
PP mode. Row and column addresses are latched during a read or
write cycle controlled by R/C# pin.
A[10:0]
R/C#
I
I
X
Row/Column Select: To indicate the row or column address in PP
mode. When this pin goes low, the row address is latched. When this
pin goes high, the column address is latched.
X
X
Data Inputs/Outputs: Used for A/A Mux mode only, to input
command/data during write operation and to output data during read
operation. The data pins float to tri-state when OE# is disabled.
I/O[7:0]
I/O
WE#
OE#
I
I
X
X
Write Enable: Activate the device for write operation. WE# is active low.
Output Enable: Control the device's output buffers during a read cycle.
OE# is active low.
Interface Configuration Select: This pin determines which mode is
selected. When pulls high, the device enters into A/A Mux mode. When
pulls low, FWH/LPC mode is selected. This pin must be setup during
power-up or system reset, and stays no change during operation. This
pin is internally pulled down with a resistor between 20-100 KΩ.
IC
I
X
X
X
X
RST#
INIT#
I
I
X
X
X
X
Reset: To reset the operation of the device and return to standby mode.
Initialize: This is a second reset pin for in-system use. INIT# or RST# pin
pulls low will initiate a device reset.
FWH/LPC General Purpose Inputs: Used to set the GPI_REG for
system design purpose only. The value of GPI_REG can be read
through FWH interface. These pins should be set at desired state
before the start of the PCI clock cycle for read operation and should
remain no change until the end of the read cycle. Unused GPI pins must
not be floated.
GPI[4:0]
I
X
X
Top Block Lock: When pulls low, it enables the hardware write protection
for top boot block. When pulls high, it disables the hardware write
protection.
TBL#
WP#
I
I
X
X
X
X
Write Protect: When pulls low, it enables the hardware write protection
to the memory array except the top boot block. When pulls high, it
disables hardware write protection.
FWH Address and Data: The major I/O pins for transmitting data,
addresses and command code in FWH mode.
FWH[3:0]
FWH4
I/O
X
X
FWH Input: To indicate the start of a FWH memory cycle operation.
Also used to abort a FHW memory cycle in progress.
I
I/O
I
LPC Address and Data: The major I/O pins for transmitting data,
addresses and command code in LPC mode.
LAD[3:0]
LFRAME#
CLK
X
X
X
LPC Frame: To indicate the start of a LPC memory cycle operation.
Also used to abort a LPC memory cycle in progress.
FWH/LPC Clock: To provide a synchronous clock for FWH and LPC
mode operations.
I
X
X
Identification Inputs: These four pins are part of the mechanism that
allows multiple FWH devices to be attached to the same bus. The
strapping of these pins is used to identify the component. The boot
device must have ID[3:0] = 0000b and it is recommended that all
subsequent devices should use sequential up-count strapping. These
pins are internally pulled-down with a resistor between 20-100 KΩ.
ID[3:0]
I
VCC
X
X
X
X
X
X
X
X
X
X
X
Device Power Supply
GND
NC
Ground
No Connection
RES
Reserved: Reserved function pins for future use.
Note: I = Input, O = Output
Programmable Microelectronics Corp.
Issue Date: December, 2003 Rev: 1.4
5
PMC [ PMC-SIERRA, INC ]
