Pm49FL002 / 004
PMC
A/A MUX MODE OPERATION
are latched on the falling edge of R/C# pin. The column
addresses (internal address A21 - A11) are latched on
the rising edge of R/C# pin. The Pm49FL002 uses A17
- A0 internally to decode and access the 256 Kbytes
memory space. The Pm49FL004 use A18 - A0 respec-
tively.
A/A MUX MODE READ/WRITE OPERATION
The Pm49FL002/004 offers a Address/Address Multi-
plexed (A/A Mux) mode for off-system operation, typi-
cally on an EPROM Programmer, similar to a traditional
Flash memory except the address input is multiplexed.
In the A/A Mux mode, the programmer must drive the
OE# pin to low (VIL) for read or WE# pins to low for write
operation. The devices have no Chip Enable (CE#) pin
for chip selection and activation as traditional Flash
memory. The R/C#, OE# and WE# pins are used to ac-
tivate the device and control the power. The 11 multiplex
address pins - A[10:0] and a R/C# pin are used to load
the row and column addresses for the target memory
location. The row addresses (internal address A10 - A0)
During a read operation, the OE# signal is used to con-
trol the output of data to the 8 I/O pins - I/O[7:0]. During
a write operation, the WE# signal is used to latch the
input data from I/O[7:0]. See Table 10 for Bus Operation
Modes.
Table 10. A/A Mux Mode Bus Operation Modes
Mode
RST#
VIH
OE#
VIL
VIH
VIH
VIH
X
WE#
VIH
VIL
VIH
X
Address
I/O
DOUT
Read
X (1)
X
Write
VIH
DIN
Standby
VIH
X
High Z
High Z
High Z
Output Disable
Reset
VIH
X
VIL
X
X
A2 - A21 = X,
A1 = VIL, A0 = VIL
and
Manufacturer ID (2)
Device ID (2)
A1 = VIH, A0 = VIH
Product Identification
VIH
VIL
VIH
A2 - A21 = X,
A1 = VIL, A0 = VIH
Notes:
1. X can be VIL or VIH.
2. Refer to Table 1 for the Manufacturer ID and Device ID of devices.
Issue Date: December, 2003 Rev: 1.4
Programmable Microelectronics Corp.
26
PMC [ PMC-SIERRA, INC ]
