Pm49FL002 / 004
PMC
LPC MODE OPERATION (CONTINUED)
LPC GPI REGISTER READ WAVEFORMS
CLK
RST# or INIT#
LFRAME#
Memory
Read
Cycle
SYNC
0000b
Address
1100b
TAR
Data
Next Start
0000b
Start
TAR
Tri-State
1111b
0000b
0000b
1111b
2
Tri-State
1111b
2
0000b
Clock
010Xb
Clock
1111b
1011b
0000b
0001b
D[3:0]
D[7:4]
LAD[3:0]
1
1
Clocks
1
Clock
Data Out
2
Clocks
Clocks
1 Clock
Load Address "FFBC0100h" in
8 Clocks
From Device to Host
From Host to Device
Issue Date: December, 2003 Rev: 1.4
Programmable Microelectronics Corp.
22