Pm49FL002 / 004
PMC
REGISTERS
BLOCK LOCKING REGISTERS
The Pm49FL002/004 have two registers include the Gen-
eral Purpose Inputs Register (GPI_REG - available in
FWH and LPC modes) and the Block Locking Register
(BL_REG - available in FWH mode only). The GPI_REG
can be read at FFBC0100h in the 4 Gbyte system
memory map. And the BL_REG can be read through
FFBx0002h where x = F - 0h. See Table 8 and 9 for the
address of BL_REG.
The devices support block read-lock, write-lock, and lock-
down features through a set of Block Locking Registers.
Each memory block has an associated 8-bit read/writ-
able block locking register. Only Bit 2 to Bit 0 are used
in current version and Bit 7 to Bit 3 are reserved for future
use. The default value of BL_REG is “01h” at power up.
The definition of BL_REG is listed in Table 7. The FWH
Register Configuration Map of Pm49FL002 is shown in
Table 8. The FWH Register Configuration Map of
Pm49FL004 is shown in Table 9. Unused register will be
read as 00h.
GENERAL PURPOSE INPUTS REGISTER
The Pm49FL002/004 contain an 8-bit General Purpose
Inputs Register (GPI_REG) available in FWH and LPC
modes. Only Bit 4 to Bit 0 are used in current version
and Bit 7 to Bit 5 are reserved for future use. The
GPI_REG is a pass-through register with the value set
by GPI[4:0] pin during power-up. The GPI_REG is used
for system design purpose only, the devices do not use
this register. This register is read only and can be read
at address location FFBC0100h in the 4 GByte system
memory map through a memory read cycle. Refer to
Table 6 for General Purpose Input Register Definition.
Table 6. General Purpose Inputs Register Definition
Bit
7:5
4
Bit Name
Function
Reserved
32-PLCC Pin#
32-VSOP Pin#
-
-
GPI4
GPI3
GPI2
GPI1
GPI0
GPI_REG Bit 4
GPI_REG Bit 3
GPI_REG Bit 2
GPI_REG Bit 1
GPI_REG Bit 0
30
3
6
3
11
12
13
14
2
4
1
5
0
6
Issue Date: December, 2003 Rev: 1.4
Programmable Microelectronics Corp.
23
PMC [ PMC-SIERRA, INC ]
