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PM49FL002T-33JC 参数 Datasheet PDF下载

PM49FL002T-33JC图片预览
型号: PM49FL002T-33JC
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位/ 4兆位3.3伏,只有固件集线器/ LPC闪存 [2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory]
分类和应用: 闪存PC
文件页数/大小: 46 页 / 208 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM49FL002T-33JC的Datasheet PDF文件第17页浏览型号PM49FL002T-33JC的Datasheet PDF文件第18页浏览型号PM49FL002T-33JC的Datasheet PDF文件第19页浏览型号PM49FL002T-33JC的Datasheet PDF文件第20页浏览型号PM49FL002T-33JC的Datasheet PDF文件第22页浏览型号PM49FL002T-33JC的Datasheet PDF文件第23页浏览型号PM49FL002T-33JC的Datasheet PDF文件第24页浏览型号PM49FL002T-33JC的Datasheet PDF文件第25页  
Pm49FL002 / 004  
PMC  
LPC BLOCK ERASE WAVEFORMS  
CLK  
RST# or INIT#  
LFRAME#  
Memory  
Write  
Address  
11xxb  
Data  
1010b  
TAR  
Sync  
TAR  
1st Start  
0000b  
Cycle  
0101b  
1010b  
0101b  
1010b  
1111b  
2
0000b  
1111b  
011Xb  
1111b  
0101b  
Clocks  
0101b  
0101b  
Tri-State  
Clocks  
Tri-State  
1111b  
1111b  
LAD[3:0]  
CLK  
1
Clock  
2
Clocks  
Device to Host  
Load "AAh" in  
2
Clocks  
1
Clock  
1
1
1
Clock  
Load "5555h" in  
8
8
8
Host to Device  
RST# or INIT#  
LFRAME#  
Memory  
Write  
Cycle  
Address  
11xxb  
Load "2AAAh" in  
Data  
0101b  
TAR  
Sync  
TAR  
1111b  
Tri-State  
Clocks  
2nd Start  
0000b  
1111b  
1111b  
1010b  
0101b  
011Xb  
Clock  
1111b  
0010b  
Clocks  
1010b  
1111b  
2
0000b  
Tri-State  
Clocks  
LAD[3:0]  
CLK  
1
Clock  
2
Load "55h" in  
2
Clocks  
1
Clock  
Host to Device  
Device to Host  
RST# or INIT#  
LFRAME#  
LAD[3:0]  
Memory  
Write  
Cycle  
Address  
11xxb  
Load "5555h" in  
Data  
0000b  
TAR  
Tri-State  
Clocks  
Sync  
TAR  
3rd Start  
0000b  
1111b  
1111b  
1000b  
1111b  
2
0000b  
1111b  
Tri-State  
011Xb  
Clock  
1111b  
0101b  
Clocks  
0101b  
0101b  
1
Clock  
2
Clocks  
Device to Host  
Load "80h" in  
2
Clocks  
1
Clock  
Host to Device  
CLK  
RST# or INIT#  
LFRAME#  
Memory  
Write  
Address  
11xxb  
0101b  
Load "5555" in 8 Clocks  
Data  
0101b  
TAR  
Sync  
TAR  
4th Start  
0000b  
Cycle  
0101b  
1111b  
1111b  
1111b  
1111b  
1111b  
1111b  
0101b  
0101b  
1010b  
Tri-State  
Clocks  
011Xb  
Clock  
1111b  
1111b  
2
0000b  
1111b  
Tri-State  
Clocks  
LAD[3:0]  
1
Clock  
2
Load "AAh" in  
2
Clocks  
1
Clock  
1
1
1
Host to Device  
Device to Host  
CLK  
RST# or INIT#  
LFRAME#  
Memory  
Write  
Cycle  
Address  
11xxb  
Load "2AAAh" in 8  
Data  
0101b  
TAR  
Tri-State  
Clocks  
Sync  
TAR  
5th Start  
0000b  
011Xb  
Clock  
1111b  
0010b  
Clocks  
1010b  
1010b  
1010b  
0101b  
1111b  
2
0000b  
1111b  
Tri-State  
LAD[3:0]  
CLK  
1
Clock  
2
Clocks  
Device to Host  
Load "55h" in  
2
Clocks  
1
Clock  
Host to Device  
RST# or INIT#  
LFRAME#  
Memory  
Write  
Cycle  
Internal Erase  
Start  
Address  
BA[19:16]  
Data  
0000b  
TAR  
Sync  
TAR  
6th Start  
0000b  
BA[15:14]  
xxxxb  
xxxxb  
xxxxb  
0101b  
Tri-State  
Clocks  
011Xb  
Clock  
1111b  
Load Block Address in  
BA  
1111b  
2
0000b  
1111b  
Tri-State  
Clocks  
LAD[3:0]  
+
xxb  
1
Clock  
2
Load "50h" in  
2 Clocks  
1
Clock  
8
Clocks  
Host to Device  
Device to Host  
=
Block Address  
Issue Date: December, 2003 Rev: 1.4  
Programmable Microelectronics Corp.  
21  
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