Pm49FL002 / 004
PMC
LPC MODE OPERATION (CONTINUED)
Table 4: LPC Memory Read Cycle Definition
Clock Cycle
Field
LAD[3:0] Direction Description
Start of Cycle: "0000b" indicates the start of a LPC memory
cycle.
1
START
0000
010x
IN
IN
Cycle Type: Indicates the type of a LPC memory read cycle.
CYCTYPE: Bits 3 - 2 must be "01b" for memory cycle. DIR:
Bit 1 = "0b" indicates the type of cycle for Read. Bit 0 is
reserved.
CYCTYPE
2
+
DIR
Address Cycles: This is the 32-bit memory address. The
addresses transfer most-significant nibble first and least-
significant nibble last. (i.e., A31 - 28 on LAD[3:0] first, and A3
- A0 on LAD[3:0] last).
3 - 10
ADDR
YYYY
1111
IN
IN then
Float
Turn-Around Cycle 0: The Chipset has driven the bus to all
"1"s and then float the bus.
11
12
13
TAR0
TAR1
SYNC
1111
(float)
Float then Turn-Around Cycle 1: The device takes control of the bus
OUT
during this cycle.
Sync: The device indicates the least-significant nibble of data
byte will be ready in next clock cycle.
0000
YYYY
1111
OUT
Data Cycles: The 8-bits data transferred with least-significant
nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on
LAD[3:0] first, then I/O7 - I/O4 on LAD[3:0] last).
14 - 15
DATA
OUT
OUT then Turn-Around Cycle 0: The device has driven the bus to all
Float "1"s and then floats the bus.
Float then Turn-Around Cycle 1: The Chipset resumes control of the bus
IN during this cycle.
16
17
TAR0
TAR1
1111
(float)
LPC MEMORY READ CYCLE WAVEFORMS
CLK
RST# or INIT#
LFRAME#
Memory
Read
Cycle
SYNC
0000b
Address
TAR
Data
Next Start
0000b
Tri-State
Start
TAR
11b
+
1111b
1111b
A[7:4]
A[3:0]
1111b
2
Tri-State
0000b
Clock
010Xb
Clock
1111b
A[15:12]
Clocks
A[11:8]
D[3:0]
D[7:4]
1111b
2
LAD[3:0]
A[17:16]
1
1
Clocks
1
Clock
Data Out
2
Clocks
1 Clock
Clocks
Load Address in
8
From Host to Device
From Device to Host
Issue Date: December, 2003 Rev: 1.4
Programmable Microelectronics Corp.
17
PMC [ PMC-SIERRA, INC ]
