PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
PMC-Sierra has verified the operation of the XPLS functional block with the
following 1:1.36 transformers:
• Pulse Engineering PE64937 (1:1.36)
• Pulse Engineering PE65340 (1:1.36) (for extended temperature range)
• BH Electronics 500-1776 (1:1.36)
Many manufacturers produce dual transformers containing the1:2 CT and 1:1.36
transformers necessary for the receiver and transmitter circuits. PMC-Sierra has
verified the operation of XPLS and RSLC with the following dual parts:
• Pulse Engineering PE64952
• Pulse Engineering PE65774 (for extended temperature range)
• BH Electronics 500-1777
8.27 BackplaneTransmit Interface (BTIF)
The Backplane Transmit Interface allows data to be taken from a backplane in
either a 1.544Mbit/s or a 2.048Mbit/s serial stream and allows BPV transparency
by accepting dual-rail data input at 1.544Mbit/s.
When configured to receive a 1.544Mbit/s data rate stream, the block expects
the input data stream on the BTPCM pin to contain 24 channel bytes of data
followed by a single bit location for the framing bit. The BTSIG input pin must
contain 24 bytes of signalling nibble data located in the least significant nibble of
each byte followed by a single bit position for the framing bit.The framing
alignment indication on the BTFP pin indicates the framing bit position of the
193-bit frame (or, optionally, the framing bit position of the first frame of the
superframe, or every second superframe).
When configured to receive a 2.048Mbit/s data rate stream, the block internally
gaps the 2.048MHz rate backplane clock to convert the serial PCM data on the
BTPCM pin containing three channel bytes of data followed by one byte of "filler"
(which can be logic "0" or logic "1") into an internal 1.544Mbit/s serial stream for
transmission.The data stream on the BTSIG pin, containing three bytes of valid
signalling nibbles (i.e. three channels' signalling contained in the least significant
nibble of each of the three byte locations) followed by one byte of "filler", is
similarly converted to an internal 1.544Mbit/s rate.The frame alignment
indication provided on the BTFP pin must go to logic "1" for one BTCLK cycle
during the first bit of the "filler" byte, indicating the next data byte is the first
channel of the frame, or the first channel of the first frame of the superframe.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
57
PMC [ PMC-SIERRA, INC ]
