PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 43H: SIGX Channel Indirect Data Buffer
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
D3
X
X
X
X
0
0
0
0
R/W
R/W
R/W
R/W
D2
D1
D0
This register contains either the data to be written into the internal SIGX registers
when a write request is initiated or the data read from the internal SIGX registers
when a read request has completed. During normal operation, if data is to be
written to the internal registers, the nibble to be written must be written into this
Data register before the target register's address and R/WB=0 is written into the
Address/Control register, initiating the access. If data is to be read from the
internal registers, only the target register's address and R/WB=1 is written into
the Address/Control register, initiating the request. After 640 ns, this register will
contain the requested data bits.
The internal registers of the SIGX control the per-channel functions on the
Receive PCM data and allow the µP to read the channel's current signalling data.
The address bit A5 selects whether a channel's configuration data register is to
be accessed (A5=1) or whether a channel's signalling data register is to be
accessed.The channel registers are allocated within the SIGX as follows:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
156
PMC [ PMC-SIERRA, INC ]
