PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 40H: SIGX Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
ESF
X
X
X
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
FMS1
FMS0
IND
PCCE
This register allows selection of the framing format, the microprocessor access
type, and allows enabling of the per-channel configuration registers.
ESF:
The framing format is controlled by the ESF, FMS1, and FMS0 bits.The ESF
bit selects either extended superframe format or enables the Frame Mode
Select bits to select either regular superframe or SLC®96 framing formats. A
logic 1 in the ESF bit position selects ESF; a logic 0 bit enables FMS1 and
FMS0 to select SF or SLC®96.
FMS1,FMS0:
The FMS1 bit selects standard Superframe or SLC®96 framing formats. A
logic 0 in the FMS1 bit enables the SF framing format; a logic 1 in the FMS1
bit position enables the SLC®96 framing format.The FMS0 bit disables the
signalling extraction and bit fixing. A logic 0 in the FMS0 bit position enables
the SIGX to provide an extracted signalling bit stream and to provide bit fixing
on the processed PCM stream; a logic 1 in the FMS0 bit position disables the
signalling extraction, forcing the signalling output stream to logic 0 and
disables bit fixing on the PCM stream.
When ESF is selected (ESF bit set to logic 1), the extended superframe
format is selected and the FMS1 and FMS0 bits are ignored.
The valid combinations of the ESF, FMS1, and FMS0 bits are summarized in the
table below:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
152
PMC [ PMC-SIERRA, INC ]
