PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
SIGX Internal Registers 21-38H: PER-CHANNEL Configuration Data
Bit
Type
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
INV
R/W
R/W
R/W
R/W
FIX
POL
DEB
INV:
The INV bit controls data inversion for the selected channel: a logic 1 in the
INV bit position enables data inversion; a logic 0 disables data inversion.
Inversion only affects the channel data, F-bits are passed unchanged.
FIX:
The FIX bit controls whether the signalling bit ( the least significant bit of the
channel byte) is fixed to the polarity specified by the POL bit. A logic 1 in the
FIX position enables bit fixing; a logic 0 in the FIX position disables bit fixing.
POL:
The POL bit selects the logic level the signalling bit is fixed to when bit fixing
is enabled. NOTE: when data inversion is selected for the channel and bit
fixing is enabled, then the sense of POL is also inverted (i.e. if inversion is
enabled and POL=1, then the bit will be fixed to logic 0).
DEB:
The DEB bit controls whether a channel's signalling bits are to be debounced.
Debouncing requires that the signalling bits be in the same state for two
successive superframes before the signalling bits are changed to that state.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
159
PMC [ PMC-SIERRA, INC ]
