PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Table 16
- SIGX Frame Format Options
ESF
FMS1
FMS0
Mode
0
0
0
1
0
1
X
X
0
0
1
X
Select Superframe framing format
Select SLC®96 framing format
Disable signalling extraction
Select ESF framing format
IND:
The IND bit controls the microprocessor access type: either indirect or direct.
The IND bit must be set to logic 1 for proper operation. When the T1XC is
reset, the IND bit is set low, disabling the indirect access mode.
PCCE:
The PCCE bit enables the per-channel functions. When the PCCE bit is set
to a logic 1, data inversion, bit fixing, and signalling debouncing are
performed on a per-channel basis. When the PCCE bit is set to logic 0, the
per-channel functions are disabled.
Upon reset of the T1XC, the ESF, FMS[1:0], IND, and PCCE bits are all set to
logic 0, selecting the Superframe framing format, disabling µP indirect access,
and disabling per-channel functions.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
153
PMC [ PMC-SIERRA, INC ]
