PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 44H: XBAS Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MTRK
Reserved
B8ZS
0
0
0
0
0
0
0
0
ESF
FMS1
FMS0
ZCS1
ZCS0
Bit 6 of the configuration register is reserved and must be set to logic 0 for proper
operation.
ZCS[1:0]:
The ZCS[1:0] bits select the Zero Code Suppression format to be used.
These bits are logically ORed with the ZCS[1:0] bits in the TPSC per-channel
PCM Control byte.The bits are encoded as follows:
Table 18
ZCS1
- XBAS Zero Code Suppression Options
ZCS0
Zero Code Suppression Format
0
0
0
1
None
GTE Zero Code Suppression ("jammed bit 8", except in
signalling frames when "jammed bit 7" is used if the
signalling bit is 0)
1
0
1
DDS Zero Code Suppression (data byte replaced with
"10011000")
1
Bell Zero Code Suppression ("jammed bit 7")
B8ZS:
The B8ZS bit enables B8ZS line coding when it is a logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
160
PMC [ PMC-SIERRA, INC ]
