PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 3AH: RFDL Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
FE
X
X
X
X
X
X
X
X
OVR
FLG
EOM
CRC
NVB2
NVB1
NVB0
NVB[2:0]:
The NVB[2:0] bit positions indicate the number of valid bits in the Receive
Data Register byte. It is possible that not all of the bits in the Receive Data
Register are valid when the last data byte is read since the data frame can be
any number of bits in length and not necessarily an integral number of bytes.
The Receive Data Register is filled from the MSB to the LSB bit position, with
one to eight data bits being valid. The number of valid bits is equal to 1 plus
the value of NVB[2:0]. A NVB[2:0] value of 000 binary indicates that only the
MSB in the register is valid. NVB[2:0] is only valid when the EOM bit is a logic
1 and the FLG bit is a logic 1 and the OVR bit is a logic 0. NVB[2:0] are set to
111 binary on reset of the T1XC.
CRC:
The CRC bit is set if a CRC error was detected in the last received LAPD
frame. The CRC bit is only valid when EOM is logic 1 and FLG is a logic 1
and OVR is a logic 0.
On an interrupt generated from the detection of first flag, reading the Status
register will return invalid NVB[2:0] and CRC bits, even though the EOM bit is
logic 1 and the FLG bit is logic 1.
EOM:
The End of Message bit (EOM) follows the RDLEOM output. It is set when:
• The last byte in the LAPD frame (EOM) is being read from the
Receive Data Register,
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
144
PMC [ PMC-SIERRA, INC ]
