PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 3BH: RFDL Receive Data
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
X
X
X
X
X
X
X
X
RD0 corresponds to the first bit of the serial byte received by the RFDL.
This register is actually a 4 level FIFO. If data is available, the FE bit in the
Status register is low. If INTC[1:0] (in the Enable/Status register) is set to 01, the
Receive Data register must be read within 31 data bit periods to prevent an
overrun. If INTC[1:0] is set to 11 the Receiver Data register must be read within
15 data bit periods.
When an overrun is detected, an interrupt is generated and the FIFO is held
cleared until the Status register is read. When the LAPD abort sequence
(01111111) is detected in the data an ABORT interrupt is generated and the
data that has been shifted into the serial to parallel converter is written into the
FIFO.
A read of the Receive Data register increments the FIFO pointer at the end of the
read. If the Receive Data register read causes an FIFO underrun, then the
pointer is inhibited from incrementing. The underrun condition will be signalled in
the next Status read by returning all zeros.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
146
PMC [ PMC-SIERRA, INC ]
