PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 39H: RFDL Interrupt Control/Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
INTC1
INTC0
INT
X
X
X
X
X
0
R/W
R/W
R
0
0
INTC1,INTC0:
The INTC1 and INTC0 bits control when an interrupt is asserted based on the
number of received data bytes in the FIFO as follows:
Table 14
- RFDL Fill Level Interrupt Options
INTC1
INTC0
Description
0
0
1
1
0
1
0
1
Disable interrupts (All sources)
Enable interrupt when FIFO receives data
Enable interrupt when FIFO has 2 bytes of data
Enable interrupt when FIFO has 3 bytes of data
INT:
The INT bit reflects the status of the external RDLINT interrupt unless the
INTC1 and INTC0 bits are set to disable interrupts. In that case, the RDLINT
output is forced to 0 and the INT bit of the Enable/Status register will reflect
the state of the internal interrupt latch.
In addition to the FIFO fill status, interrupts are also generated for EOM (end of
message), OVR (FIFO overrun), detection of the abort sequence while not
receiving all ones and on detection of the first flag while receiving all ones. The
interrupt is reset by a Receive Data Register read that empties the FIFO, unless
the cause of the interrupt was due to a FIFO overrun. The interrupt due to a
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
142
PMC [ PMC-SIERRA, INC ]
