PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 3CH: IBCD Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
ACCEL
Unused
Unused
Unused
DSEL1
DSEL0
ASEL1
ASEL0
0
X
X
X
0
0
0
0
R/W
R/W
R/W
R/W
This register provides the selection of the Activate and De-activate loopback
code lengths (from 3 bits to 8 bits) as follows:
Table 15
- IBCD Code Length Options
DEACTIVATE
Code
ACTIVATE
Code
DSEL1
DSEL0
ASEL1
ASEL0
CODE LENGTH
5 bits
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
6 (or 3*) bits
7 bits
8 (or 4*) bits
*Note: 3 and 4 bit code sequences can be accommodated by configuring the
IBCD for 6 or 8 bits and by programming two repetitions of the code sequence.
The ACCEL bit is used for production test purposes only.THE ACCEL BIT MUST
BE PROGRAMMED TO LOGIC 0 FOR NORMAL OPERATION.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
147
PMC [ PMC-SIERRA, INC ]
