PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 2DH: ALMI Interrupt Enable
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
FASTD
ACCEL
YELE
X
X
X
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
REDE
AISE
This register selects which of the three CFA's can generate an interrupt when
their logic state changes and enables the "fast" deassertion mode of operation.
FASTD:
The FASTD bit enables the "fast" deassertion of RED and AIS alarms. When
FASTD is set to a logic 1, deassertion of RED alarm occurs within 120 ms of
going in frame. Deassertion of AIS alarm occurs within 180 ms of either
detecting a 60 ms interval containing 127 or more zeros, or going in frame.
When FASTD is set to a logic 0, RED and AIS alarm deassertion times
remain as defined in the ALMI description.
ACCEL:
The ACCEL bit is used for production test purposes only.THE ACCEL BIT
MUST BE PROGRAMMED TO LOGIC 0 FOR NORMAL OPERATION.
YELE,REDE,AISE:
A logic 1 in the enable bit positions (YELE, REDE, AISE) enables a state
change in the corresponding CFA to generate an interrupt; a logic 0 in the
enable bit positions disables any state changes to generate an interrupt. The
enable bits are independent; any combination of YELLOW, RED, and AIS
CFA's can be enabled to generate an interrupt.
Upon reset of the T1XC, these bits are cleared to logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
124
PMC [ PMC-SIERRA, INC ]
