PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 0BH:T1XC MasterTest
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
PMCTST
DBCTRL
IOTST
X
X
X
X
0
W
W
R/W
W
0
HIZDATA
HIZIO
0
R/W
0
This register is used to select T1XC test features. All bits, except for PMCTST,
are reset to zero by a hardware reset of the T1XC ; a software reset of the T1XC
does not affect the state of the bits in this register.
PMCTST:
The PMCTST bit is used to configure the T1XC for PMC's manufacturing
tests. When PMCTST is set to logic 1, the T1XC microprocessor port
becomes the test access port used to run the PMC manufacturing test
vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and can only
be cleared by setting CSB to logic 1.
DBCTRL:
The DBCTRL bit is used to pass control of the data bus drivers to the CSB
pin. When the DBCTRL bit is set to logic 1, the CSB pin controls the output
enable for the data bus. While the DBCTRL bit is set, holding the CSB pin
high causes the T1XC to drive the data bus and holding the CSB pin low tri-
states the data bus. The DBCTRL bit overrides the HIZDATA bit. The
DBCTRL bit is used to measure the drive capability of the data bus driver
pads.
IOTST:
The IOTST bit is used to allow normal microprocessor access to the test
registers and control the test mode in each block in the T1XC for board level
testing. When IOTST is a logic 1, all blocks are held in test mode and the
microprocessor may write to a block's test mode 0 registers to manipulate the
outputs of the block and consequently the device outputs (refer to the "Test
Mode 0 Details" in the "Test Features" section).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
90
PMC [ PMC-SIERRA, INC ]
