STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
In the address matching mode, only those packets whose first data byte matches
one of two programmable bytes or the universal address (all ones) are stored in
the FIFO. The two least significant bits of the address comparison can be
masked for LAPD SAPI matching.
Received data is placed into a 128-level FIFO buffer. An interrupt is generated
when a programmable number of bytes are stored in the FIFO buffer. Other
sources of interrupt are detection of the terminating flag sequence, abort
sequence, or FIFO buffer overrun.
The Status Register contains bits which indicate the overrun or empty FIFO
status, the interrupt status, and the occurrence of first flag or end of message
bytes written into the FIFO. The Status Register also indicates the abort, flag,
and end of message status of the data just read from the FIFO. On end of
message, the Status Register indicates the FCS status and if the packet
contained a non-integer number of bytes.
9.6 T1 Alarm Integrator (ALMI)
The T1 Alarm Integration function is provided by the ALMI block. This block
detects the presence of Yellow, Red, and AIS Carrier Fail Alarms (CFA) in SF, or
ESF formats. The alarm detection and integration is compatible with the
specifications defined in ANSI T1.403 and TR-TSY-000191.
The ALMI block declares the presence of Yellow alarm when the Yellow pattern
has been received for 425 ms (± 50 ms); the Yellow alarm is removed when the
Yellow pattern has been absent for 425 ms (± 50 ms). The presence of Red
alarm is declared when an out-of-frame condition has been present for 2.55 sec
(± 40 ms); the Red alarm is removed when the out-of-frame condition has been
absent for 16.6 sec (± 500 ms). The presence of AIS alarm is declared when an
out-of-frame condition and all-ones in the PCM data stream have been present
for 1.5 sec (±100 ms); the AIS alarm is removed when the AIS condition has
been absent for 16.8 sec (±500 ms).
-3
CFA alarm detection algorithms operate in the presence of a 10 bit error rate.
The ALMI also indicates the presence or absence of the Yellow, Red, and AIS
alarm signal conditions over 40 ms, 40 ms, and 60 ms intervals, respectively,
allowing an external microprocessor to integrate the alarm conditions via
software with any user-specific algorithms. Alarm indication is provided through
internal register bits.
PROPRIETARY AND CONFIDENTIAL
64
PMC [ PMC-SIERRA, INC ]
