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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
holding registers and resets the counters to begin accumulating events for the  
interval. The counters are reset in such a manner that error events occurring  
during the reset are not missed. If the holding registers are not read between  
successive transfer clocks, an OVERRUN register bit is asserted.  
Generation of the transfer clock within the TECT3 chip is performed by writing to  
any counter register location or by writing to the Global PMON Update register.  
The holding register addresses are contiguous to facilitate faster polling  
operations.  
9.4 Bit Oriented Code Detector (RBOC)  
The Bit Oriented Code detection function is provided by the RBOC block. This  
block detects the presence of 63 of the possible 64 bit oriented codes  
transmitted in the T1 Facility Data Link channel in ESF framing format, as  
defined in ANSI T1.403 and in TR-TSY-000194 or in the DS3 C-bit parity far-end  
alarm and control (FEAC) channel. The 64Th code (111111) is similar to the  
HDLC flag sequence and is used by the RBOC to indicate no valid code  
received.  
Bit oriented codes are received on the Facility Data Link channel or FEAC  
channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a  
trailing zero (111111110xxxxxx0). BOCs are validated when repeated at least 10  
times. The RBOC can be enabled to declare a received code valid if it has been  
observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit  
in the RBOC Configuration/Interrupt Enable register. The RBOC declares that  
the code is removed if two code sequences containing code values different from  
the detected code are received in a moving window of ten code periods.  
Valid BOC are indicated through the RBOC Interrupt Status register. The BOC  
bits are set to all ones (111111) if no valid code has been detected. An interrupt  
is generated to signal when a detected code has been validated, or optionally,  
when a valid code goes away (i.e. the BOC bits go to all ones).  
9.5 HDLC Receiver (RDLC)  
The RDLC is a microprocessor peripheral used to receive HDLC frames on the  
4kHz ESF facility data link, the E1 Sa-bit data link, the DS3 C-bit parity Path  
Maintenance Data Link or a specified channel within a T1 or E1 stream.  
The RDLC detects the change from flag characters to the first byte of data,  
removes stuffed zeros on the incoming data stream, receives packet data, and  
calculates the CRC-CCITT frame check sequence (FCS).  
PROPRIETARY AND CONFIDENTIAL  
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