STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
5.2 M13 Multiplexer Mode Block Diagram
Figure 4 shows the TECT3, configured as a M13 multiplexer, connected to a
synchronous H-MVIP system side bus. In this example the TECT3 provides
synchronous access to the fully channelized T1s (access to all DS0s)
multiplexed into the DS3. There is also synchronous H-MVIP access to all
channel associated signaling channels (CAS). An additional H-MVIP interface
can be used to provide synchronous access to the common channel signaling
channels (CCS), although this same information is available within the data H-
MVIP signals.
Figure 4: M13 Multiplexer Block Diagram
XCLK
CTCLK
CMV8MCLK
CMVFPB
MVED[1:7]
CASED[1:7]
CCSED
TOPS
T1-XBAS/E1-TRAN
BasicTransmitter:
Frame Generation,
Alarm Insertion,
TPSC
Timing Options
ESIF
Per-DS0
Controller
Egress
System
Interface
TJAT
Signaling Insertion,
Trunk Conditioning
Digital Jitter
Attenuator
XBOC
TDPR
HDLC
Bit Oriented
Code
Transmitter
Generator
PRBS
Pattern
Gener-
ator/
PMON
Performance
Monitor
RDLC
T1-APRM
Auto
Detector
HDLC
Receiver
Performance
Response
Monitor
Counters
RBOC
Bit Oriented
Code
ALMI
Alarm
Integrator
XBOC
Tx
TDPR
Tx
Detector
HDLC
FEAC
TICLK
TCLK
TPOS/TDAT
TNEG/TMFP
#1
MVID[1:7]
CASID[1:7]
CCSID
TRAN
B3ZS
Encode
DS3
ISIF
T1/E1-FRMR
Frame
Transmit
Framer
Ingress
System
Interface
FRMR MX12
MX23
RJAT
Alignment,
Alarm
M12
DS2
Digital Jitter
Attenuator
M23
RPSC
MUX/
Framer
Extraction
SIGX
MUX/
Per-DS0
DEMUX
Signaling
Extractor
Controller
DEMUX
FRMR
DS3
Receive
ELST
Elastic
Store
B3ZS
Decode
RCLK
RPOS/RDAT
RNEG/RLCV
One of Seven
FRMR/M12s
FRAM
CIFP
CICLK/CMVFPC
Framer
Framer RAM
One of 28 T1 or
21 E1 Framers
PMON
Perf.
RBOC
Rx
FEAC
RDLC
Rx
RECVCLK1
RECVCLK2
Monitor
HDLC
5.3 DS3 Framer Only Block Diagram
Figure 5 shows the TECT3 configured as a DS3 framer. In this mode the TECT3
provides access to the full DS3 unchannelized payload. The payload access
(right side of diagram) has two clock and data interfacing modes, one utilizing a
gapped clock to mask out the DS3 overhead bits and the second utilizing an
ungapped clock with overhead indications on a separate overhead signal. The
SBI bus can also be used to provide access to the unchannelized DS3.
PROPRIETARY AND CONFIDENTIAL
18
PMC [ PMC-SIERRA, INC ]
