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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
Sꢀ Provides seven 8Mb/s H-MVIP interfaces for synchronous access to all  
channel associated signaling (CAS) bits for all T1 DS0s or E1 timeslots. The  
CAS bits occupy one nibble of every byte on the H-MVIP interfaces and are  
repeated over the entire T1 or E1 multi-frame.  
Sꢀ Provides a single 8Mb/s H-MVIP interface for common channel signaling  
(CCS) channels as well as V5.1 and V5.2 channels. In T1 mode DS0 24 is  
available through this interface. In E1 mode timeslots 15, 16 and 31 are  
available through this interface.  
Sꢀ All links accessed via the H-MVIP interface will be synchronously timed to the  
common H-MVIP clock and frame alignment signals, CMV8MCLK, CMVFP,  
CMVFPC.  
Sꢀ H-MVIP access for Channel Associated Signaling is available with the  
Scaleable Bandwidth Interconnect bus as an optional replacement for CAS  
access over the SBI bus as well as with the H-MVIP data interface. Common  
Channel Signaling H-MVIP access is available with the SBI bus, serial PCM  
and H-MVIP data interfaces.  
Sꢀ Compatible with H-MVIP PCM backplanes supporting 8.192 Mbit/s.  
Scaleable Bandwidth Interconnect (SBI) Bus:  
Sꢀ Provides a high density byte serial interconnect for all framed and unframed  
TECT3 links. Utilizes an Add/Drop configuration to asynchronously mutliplex  
up to 84 T1s or 3 DS3s, equivalent to three TECT3s, with multiple payload or  
link layer processors.  
Sꢀ External devices can access unframed DS3, framed unchannelized DS3,  
unframed (clear channel) T1s or framed T1s over this interface.  
Sꢀ Framed and unframed T1 access can be selected on a per T1 basis.  
Sꢀ Synchronous access for T1 DS0 channels is supported in a locked format  
mode.  
Sꢀ Channel associated signaling bits for channelized T1 are explicitly identified  
across bus.  
Sꢀ Transmit timing is mastered either by the TECT3 or a layer 2 device  
connecting to the SBI bus. Timing mastership is selectable on a per tributary  
basis, where a tributary is either an individual T1 or a DS3.  
PROPRIETARY AND CONFIDENTIAL  
10  
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