PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 001H: Global Configuration / Clock Monitor
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
R
XCLKA
REFCLKA
X
X
0
0
0
R
R/W
R/W
R/W
SIMUL_REGWR
SBI_SYNCH
RSYNC_SEL[2] /
ELST_SEL[2]
Bit 2
Bit 1
R/W
R/W
R/W
RSYNC_SEL[1] /
ELST_SEL[1]
0
0
0
RSYNC_SEL[0] /
ELST_SEL[0]
Bit 0
E1/T1B
XCLKA:
The XCLK active (XCLKA) bit detects low to high transitions on the XCLK input. XCLKA is
set high on a rising edge of XCLK, and is set low when this register is read. A lack of
transitions is indicated by the register bit reading low. This register bit may be read at
periodic intervals to detect clock failures.
REFCLKA:
The REFCLK active (REFCLKA) bit detects low to high transitions on the REFCLK input.
REFCLKA is set high on a rising edge of REFCLK, and is set low when this register is read.
A lack of transitions is indicated by the register bit reading low. This register bit may be read
at periodic intervals to detect clock failures.
SIMUL_REGWR:
The Simultaneous Register Write (SIMUL_REGWR) bit enables registers for all 8 octants to
be written simultaneously. When SIMUL_REGWR is set high, a write to an octant register will
result in the same data also being written simultaneously to the corresponding registers
belonging to the other 7 octants. When SIMUL_REGWR is set low, a write to a register will
result in the addressed register, and that register only, being written.
Note – SIMUL_REGWR must be set low prior to reading any OCTLIU register.
SBI_SYNCH:
The SBI Synchronous Mode (SBI_SYNCH) bit configures the INSBI to operate in SBI
Synchronous mode when set to 1. Synchronous mode should only be selected when the
device is operating as a SBI to clk/data converter (SBI2CLK input tied high). When operating
in synchronous mode, the ICLK_OUT and IFP_OUT outputs must be used as clock and
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
59
PMC [ PMC-SIERRA, INC ]
