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PM4318 参数 Datasheet PDF下载

PM4318图片预览
型号: PM4318
PDF下载: 下载PDF文件 查看货源
内容描述: 八进制E1 / T1 / J1线路接口设备 [OCTAL E1/T1/J1 LINE INTERFACE DEVICE]
分类和应用:
文件页数/大小: 244 页 / 2135 K
品牌: PMC [ PMC-SIERRA, INC ]
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PRELIMINARY  
PM4318 OCTLIU  
DATASHEET  
PMC- 2001578  
ISSUE 3  
OCTAL E1/T1/J1 LINE INTERFACE DEVICE  
8
PIN DESCRIPTION  
By convention, where a bus of eight pins indexed [8:1] is present, the index indicates to which  
octant the pin applies. With TCLK[8:1], for example, TCLK[1] applies to octant #1, TCLK[2]  
applies to octant #2, etc.  
Pin Name  
Type  
Pin  
No.  
Function  
T1 and E1 System Side Serial Clock and Data Interface  
TCLK[1]/IDATA[1]  
TCLK[2]/IDATA[2]  
TCLK[3]/IDATA[3]  
TCLK[4]/IDATA[4]  
TCLK[5]/IDATA[5]  
TCLK[6]/IDATA[6]  
TCLK[7]/IDATA[7]  
TCLK[8]/IDATA[8]  
Input  
U19  
The Transmit Clock inputs (TCLK[8:1]) should be 1.544 MHz for  
DS1 or 2.048 MHz for E1 data streams and are used to sample  
W20  
AA22 the corresponding TDP[8:1] and TDN[8:1] signals.  
AA20  
TCLK[8:1] share the same pins as the IDATA[8:1] inputs.  
TCLK[8:1] are selected when SBI2CLK is tied low.  
W2  
V3  
U4  
V1  
TDP[1]/ADATA[0]  
TDP[2]/ADATA[1]  
TDP[3]/ADATA[2]  
TDP[4]/ADATA[3]  
TDP[5]/ADATA[4]  
TDP[6]/ADATA[5]  
TDP[7]/ADATA[6]  
TDP[8]/ADATA[7]  
Input  
W22  
V19  
Y21  
Y19  
Y2  
Transmit Positive Data (TDP[8:1]). When in single-rail mode,  
these inputs are the NRZ data signals to be transmitted. These  
inputs can be configured to be active high or active low. When in  
dual-rail mode, these inputs are the NRZ positive data signals to  
be transmitted.  
Y1  
TDP[8:1] can be sampled on either the rising or falling edges of  
the corresponding TCLK[8:1].  
W1  
U2  
TDP[8:1] share the same pins as the ADATA[7:0] inputs.  
TDP[8:1] are selected when SBI_EN and SBI2CLK are both tied  
low.  
TDN[1]/REFCLK  
TDN[2]/AC1FP  
TDN[3]/DC1FP  
TDN[4]/ADP  
Input  
W21  
Y22  
Transmit Negative Data (TDN[8:1]). When in dual-rail mode,  
these inputs are the NRZ negative data signals to be transmitted.  
AA21 These inputs can be sampled on either the rising or falling edges  
W18  
AA1  
V4  
V2  
U3  
of the corresponding TCLK[8:1]. These input pins are ignored if  
the device is configured for single-rail (unipolar) transmit mode.  
TDN[5]/APL  
TDN[6]/AV5  
TDN[7]/ICLK_IN  
TDN[8]/IFP_IN  
TDN[8:1] share the same pins as the REFCLK, AC1FP, DC1FP,  
ADP, APL, AV5, ICLK_IN and IFP_IN inputs. TDN[8:1] are  
selected when SBI_EN and SBI2CLK are both tied low.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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