PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
mode / FFH in E1 mode to correctly attenuate the jitter on the receive clock. Conceptually, the
data flow through a single octant of the OCTLIU in this loopback mode is illustrated in Figure 18.
Figure 18 – Line Loopback
TDP[n]
TXTIP[x]
TDN[n]
XIBC
XPDE
IBCD
LCODE
PDVD
TJAT
XLPG
TXRING[x]
TCLK[n]
Line Loopback
RLPS
RDP[n]
RDN/RLCV[n]
RCLK[n]
RXTIP[x]
RJAT
CDRC
RXRING[x]
12.7.2 Diagnostic Digital Loopback
When Diagnostic Digital loopback (DDLB) mode is initiated by setting the DDLB bit in the Line
Interface Diagnostics Register to logic 1, the OCTLIU octant is configured to internally direct the
output of the TJAT to the inputs of the receiver section. The dual-rail RZ outputs of the TJAT are
directed to the dual-rail inputs of the CDRC. Conceptually, the data flow through a single octant
of the OCTLIU in this loopback condition is illustrated in Figure 19.
Figure 19 – Diagnostic Digital Loopback
TDP[n]
TXTIP[x]
TDN[n]
XIBC
XPDE
LCODE
PDVD
TJAT
XLPG
RLPS
TXRING[x]
TCLK[n]
Diagnostic Loopback
RDP[n]
RDN/RLCV[n]
RCLK[n]
RXTIP[x]
RJAT
CDRC
IBCD
RXRING[x]
12.8 JTAG Support
The OCTLIU supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1
standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS,
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
202
PMC [ PMC-SIERRA, INC ]
