PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
RAM Address Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
110D
111D
112D
113D
114D
115D
116D
117D
118D
119D
120D
121D
122D
123D
124D
125D
126D
127D
7274F93BH
7274F93BH
7272F93BH
7272F93BH
7272F93BH
7A72F93BH
7A70F93BH
7A70E93BH
7A78E93BH
7A78E93BH
8278E93BH
8278E93BH
8278E8BBH
8278E8BBH
8278E8BBH
8A78E8BBH
8A78E93BH
8A78F93BH
238D
239D
240D
241D
242D
243D
244D
245D
246D
247D
248D
249D
250D
251D
252D
253D
254D
255D
F8D9D7BBH
F8D9E7BBH
F8D9E3BBH
F8D9E3BBH
F8D9E3BBH
F8D9E3BBH
F8D9E3BBH
F8D9F3BBH
F8D9F3BBH
F8D9F3BBH
F8D9F3BBH
F8D9F3BBH
F8D9F3BBH
F8D9F3BBH
F8D9F3BBH
F8D9F3BBH
F8D9F3BBH
F8D9F3BBH
Table 42 – RLPS Equalizer RAM Table (Monitor Mode)
TBD
12.6 Using the PRBS Generator and Detector
PRBS patterns may be generated and detected in either the transmit or receive directions, as
configured by the TX_GEN, RX_GEN and TX_DET bits of the Line Interface PRBS Position
registers.
12.7 Loopback Modes
The OCTLIU provides two loopback modes to aid in network and system diagnostics. The
network (line) loopback can be initiated at any time via the µP interface, but is usually initiated
once an inband loopback activate code is detected. The system Diagnostic Digital loopback can
be initiated at any time by the system via the µP interface to check the path of system data
through the LIU.
12.7.1 Line Loopback
When LINE loopback (LINELB) is initiated by setting the LINELB bit in the Line Interface
Diagnostics Register to logic 1, the LIU is configured to internally connect the recovered data to
the transmit jitter attenuator, TJAT. The data sent to the TJAT is the recovered data from the
output of the CDRC block. Note that when line loopback is enabled, the contents of the TJAT
Reference Clock Divisor and Output Clock Divisor registers should be programmed to 2FH in T1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
201
PMC [ PMC-SIERRA, INC ]
