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PM4318 参数 Datasheet PDF下载

PM4318图片预览
型号: PM4318
PDF下载: 下载PDF文件 查看货源
内容描述: 八进制E1 / T1 / J1线路接口设备 [OCTAL E1/T1/J1 LINE INTERFACE DEVICE]
分类和应用:
文件页数/大小: 244 页 / 2135 K
品牌: PMC [ PMC-SIERRA, INC ]
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PRELIMINARY  
PM4318 OCTLIU  
DATASHEET  
PMC- 2001578  
ISSUE 3  
OCTAL E1/T1/J1 LINE INTERFACE DEVICE  
TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB  
input is the active-low reset signal used to reset the TAP controller. TCK is the test clock used to  
sample data on the TDI primary input and to output data on the TDO primary output. The TMS  
primary input is used to direct the TAP controller through its states. The basic boundary scan  
architecture is shown below.  
Figure 20 – Boundary Scan Architecture  
Boundary Scan  
TDI  
Register  
Device Identification  
Register  
Bypass  
Register  
Instruction  
Register  
and  
Mux  
DFF  
TDO  
Decode  
Control  
TMS  
Test  
Access  
Port  
Select  
Tri-state Enable  
Controller  
TRSTB  
TCK  
The boundary scan architecture consists of a TAP controller, an instruction register with  
instruction decode, a bypass register, a device identification register and a boundary scan  
register. The TAP controller interprets the TMS input and generates control signals to load the  
instruction and data registers. The instruction register with instruction decode block is used to  
select the test to be executed and/or the register to be accessed. The bypass register offers a  
single-bit delay from primary input, TDI to primary output, TDO. The device identification register  
contains the device identification code.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
203