PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
112D
113D
114D
115D
116D
117D
118D
119D
120D
121D
122D
123D
124D
125D
126D
127D
5E67283BH
6667283BH
6665283BH
6665283BH
6665283BH
6663283BH
6663283BH
6E63283BH
6E6B283BH
6E6B28BBH
6E6B2CBBH
6E732CBBH
6E732CBBH
76732CBBH
767328BBH
767338BBH
240D
241D
242D
243D
244D
245D
246D
247D
248D
249D
250D
251D
252D
253D
254D
255D
FCB9D2BBH
FCB9D2BBH
FCB9D2BBH
FCB9E2BBH
FCB9E2BBH
FCB9E2BBH
FCB9E2BBH
FCB9E2BBH
FCB9E2BBH
FCB9E2BBH
FCB9E2BBH
FCB9E2BBH
FCB9F2BBH
FCB9F2BBH
FCB9F2BBH
FCB9F2BBH
Table 41 – RLPS Equalizer RAM Table (E1 mode)
RAM Address Content (MSB..LSB) RAM Address
Content (MSB..LSB)
00D
01D
02D
03D
04D
05D
06D
07D
08D
09D
10D
11D
12D
13D
14D
15D
16D
17D
18D
19D
20D
21D
22D
23D
03062C3BH
03062C3BH
03062C3BH
03062C3BH
030E2C3BH
030E2C3BH
03162C3BH
03162C3BH
03162C3BH
03163C3BH
031E3C3BH
031E3C3BH
031E3C3BH
031E3C3BH
031E3C3BH
031E4C3BH
031E4C3BH
031E4C3BH
031E4C3BH
031E4C3BH
03264C3BH
03264C3BH
032E4C3BH
032E4C3BH
128D
129D
130D
131D
132D
133D
134D
135D
136D
137D
138D
139D
140D
141D
142D
143D
144D
145D
146D
147D
148D
149D
150D
151D
8A80F93BH
8A80F9BBH
8A80F9BBH
9280F9BBH
928109BBH
918109BBH
918119BBH
918119BBH
998129BBH
998125BBH
998135BBH
998135BBH
998131BBH
A18131BBH
A18931BBH
A18931BBH
A18931BBH
A19131BBH
A19131BBH
A99131BBH
A99131BBH
A991323BH
A991323BH
A991323BH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
198
PMC [ PMC-SIERRA, INC ]
