PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 077H, 0F7H, 177H, 1F7H, 277H, 2F7H, 377H, 3F7H: RLPS Equalizer Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
VALID_PER[1]
VALID_PER[0]
Unused
0
0
X
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
Reserved
EQ_EN
EQ_FREQ[2]
EQ_FREQ[1]
EQ_FREQ[0]
EQ_FREQ[2:0]:
The EQ_FREQ[2:0] field selects the frequency of the EQ feedback loop as indicated by Table
16.
Table 16 – Equalization Feedback Frequencies
EQ_FREQ[2:0]
EQ Feedback Frequency
How Frequency
Derived
T1 mode
24.125 kHz
12.063 kHz
8.0417 kHz
6.0313 kHz
4.8250 kHz
4.0208 kHz
3.4464 kHz
3.0156 kHz
E1 mode
32.000 kHz
16.000 kHz
10.667 kHz
8.0000 kHz
6.40 kHz
000
001
010
011
100
101
110
111
Line rate ÷ 64
Line rate ÷ 128
Line rate ÷ 192
Line rate ÷ 256
Line rate ÷ 320
Line rate ÷ 384
Line rate ÷ 448
Line rate ÷ 512
5.333 kHz
4.5714 kHz
4.0 kHz
EQ_EN:
The EQ_EN bit enables operation of the equaliser when set to logic 1. This bit defaults to
logic 0 after reset and must be set to logic 1, but only after the equalisation RAM has been
initialised.
Reserved:
This bit must be programmed to logic 0 for normal operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
161
PMC [ PMC-SIERRA, INC ]
