PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 073H, 0F3H, 173H, 1F3H, 273H, 2F3H, 373H, 3F3H: RLPS ALOS Clearance Period
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CLR_PER[7]
CLR_PER[6]
CLR_PER[5]
CLR_PER[4]
CLR_PER[3]
CLR_PER[2]
CLR_PER[1]
CLR_PER[0]
0
0
0
0
0
0
0
1
CLR_PER[7:0]:
This register specifies the time duration that the equalised cable loss has to remain below the
clearance threshold in order for the ALOS to be cleared. This duration is equal to CLR_PER *
16 number of pulse intervals resulting in a range from 16 to 4080 and thus compliant with all
the presently available E1/T1 ALOS clearance standards/ recommendations.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
157
PMC [ PMC-SIERRA, INC ]
