PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 074H, 0F4H, 174H, 1F4H, 274H, 2F4H, 374H, 3F4H:
RLPS Equalization Indirect Address
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EQ_ADDR[7]
EQ_ADDR[6]
EQ_ADDR[5]
EQ_ADDR[4]
EQ_ADDR[3]
EQ_ADDR[2]
EQ_ADDR[1]
EQ_ADDR[0]
0
0
0
0
0
0
0
0
EQ_ADDR [7:0]:
Writing to this register initiates an internal uP access request cycle to the RAM. Depending on
the setting of the RWB bit inside the RLPS Equalization Read/WriteB Select, a read or a write
will be performed. During a write cycle, the indirect data bits located in the RLPS
Equalization Indirect Data registers are written into the RAM. For a read request, the content
of the addressed RAM location is written into the RLPS Equalization Indirect Data registers.
This register should be the last register to be written for a uP access.
A waiting period of at least three line rate cycles is needed from when this register is written
until the next indirect data bits are written into any of the respective octant’s RLPS
Equalization Indirect Data registers.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
158
PMC [ PMC-SIERRA, INC ]
