PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
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When FIFO_UDRE is a ‘0’ underrun interrupt generation is disabled.
When FIFO_UDRE is a ‘1’ underrun interrupt generation is enabled.
FIFO_OVRE:
The FIFO_OVRE bit is used to enable/disable the generation of an interrupt when a FIFO
overrun is detected.
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When FIFO_OVRE is a ‘0’ overrun interrupt generation is disabled.
When FIFO_OVRE is a ‘1’ overrun interrupt generation is enabled.
DC_INT_EN:
This bit is set to enable the generation of an interrupt when either of the following events
occurs:
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A Depth Check error
An external resynchronization event occurs on the AC1FP signal
DC_ENBL:
This bit enables depth check resets. The depth checker periodically monitors the link FIFO
depths and compares them against the read and write pointers. Discrepancies are reported in
the Depth Checker Interrupt Status Register. If DC_ENBL is ‘1’, the affected link is
automatically reset. If DC_ENBL is ‘0’, the link is not reset.
APAGE:
The tributary mapping active page select bit (APAGE) controls the group of mapping registers
used to associate SBI tributaries and LIU octant data streams. When mapping is enabled
and APAGE is low, the A set of mapping registers (0x3A8 to 0x3AF) is used. When mapping
is enabled and APAGE is high, the B set of mapping registers (0x3B0 to 0x3B7) is used.
When APAGE changes state, any data streams where the mapping registers do not match
are automatically reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
