PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 393H: EXSBI Parity Error Interrupt Reason
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
SPE[1]
SPE[0]
TRIB[4]
TRIB[3]
TRIB[2]
TRIB[1]
TRIB[0]
PERRI
0
0
0
0
0
0
0
0
PERRI:
When set PERRI indicates that an SBI parity error has been detected. It is cleared when the
register is read.
TRIB[4:0] and SPE[1:0]:
The TRIB[4:0] and SPE[1:0] field are used to specify the SBI tributary for which a parity error
was detected. These fields are only valid only when PERRI is set. When a parity error has
not been detected the TRIB[4:0] field may contain an out of range tributary value.
If the type of the SPE where the parity error occurred does not correspond to the operating
mode of the OCTLIU (e.g. a parity error in a SPE containing E1s when the OCTLIU is
operating in T1 mode), SPE[1:0] will be valid but TRIB[4:0] will be invalid.
Values in these fields should only be looked at when PERRI is a ‘1’.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
98
PMC [ PMC-SIERRA, INC ]
