PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 332H: INSBI Master Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
X
X
0
X
0
0
X
0
R
DCR_INTI_SHDW
Unused
R
R
FIFO_UDRI_SHDW
FIFO_OVRI_SHDW
Unused
R
C1FP_SYNC_INTI
C1FP_SYNC_INTI:
This bit is set when a DC1FP realignment has been detected. It is cleared when the register
is read.
FIFO_OVRI_SHDW:
This bit is a shadow of the FIFO_OVRI bit in the INSBI FIFO Over Run Interrupt Status
Register. It is set when the FIFO_OVRI bit is set and the interrupt enable FIFO_OVRE is set.
Reading this register has no affect on the interrupt status.
FIFO_UDRI_SHDW:
This bit is a shadow of the FIFO_UDRI bit in the INSBI FIFO Under Run Interrupt Status
Register. It is set when the FIFO_UDRI bit is set and the interrupt enable FIFO_UDRE is set.
Reading this register has no affect on the interrupt status.
DCR_INTI_SHDW:
This bit is a shadow of the DCR_INTI bit in the INSBI Depth Check Interrupt Status Register.
It is set when the DCR_INTI bit is set and the interrupt enable DCR_INT_EN is set. Reading
this register has no affect on the interrupt status.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
93
PMC [ PMC-SIERRA, INC ]
