PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Figure 11
- E1 JitterTolerance
100
40
35
DJAT
minimum
10
Jitter
Amplitude,
tolerance
1. 5
UI pp
1.0
acceptable
ITU-T G.82 3
unacce ptab le
Region
0.2
0.1
0.01
2.4k
18k
20
1
100
1k
10k
100k
10
Jitter F req uency, Hz
The accuracy of the XCLK frequency and that of the DJAT PLL reference input
clock used to generate the "jitter-free" clock have an effect on the minimum jitter
tolerance. For DSX-1 interfaces, the DJAT PLL reference clock accuracy can be
±130 Hz from 1.544 MHz, and the XCLK input accuracy can be ±100 ppm from
37.056 MHz. For E1 interfaces, the PLL reference clock accuracy can be ± 50
Hz from 2.048 MHz, and the XCLK input accuracy can be ±50 ppm from 49.152
MHz. The minimum jitter tolerance for various differences between the frequency
of PLL reference clock and XCLK ÷ 24 are shown in Figure 12 and Figure 13.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
44
PMC [ PMC-SIERRA, INC ]
