February, 2007
Sample Configuration Procedure
The sequence executed to set up and initialize a PEX 8532 switch is as follows:
1. Ports and lanes, per port:
• Refer to Section 4.1.2.1, “Port Combinations,” for options
• PEX 8532 must be connected to PCI Express-compatible devices
• Strapping balls must be set to identify the selected port configuration
– For Station 0, refer to STRAP_STN0_PORTCFG[4:0]
– For Station 1, refer to STRAP_STN1_PORTCFG[4:0]
• Serial EEPROM overrides the Strapping ball selections
2. Select the upstream port – Set Strapping balls STRAP_UPSTRM_PORTSEL[3:0].
3. Software/serial EEPROM programs the following registers for the upstream port:
• Primary Bus Number – Identifies the upstream link (Bus Number register, offset 18h[7:0])
• Secondary Bus Number – Identifies the switch internal Virtual PCI Bus
(Bus Number register, offset 18h[15:8])
• Subordinate Bus Number – Must be the last (largest) Bus Number in the downstream
hierarchy of this upstream port (Bus Number register, offset 18h[23:16])
• Set the Command register Bus Master Enable and Memory Access Enable bits
(offset 04h[2:1], respectively)
• Base and Limit registers – Combines the memory of all downstream devices into one
large space, with the total size given by Limit - Base, and the Start address given by Base
• Base Address 0 and Base Address 1 registers (BAR0 and BAR1, offsets 10h and 14h,
respectively) (Base address for Memory-Mapped CSR access on the PEX 8532)
4. Software/serial EEPROM programs the following registers for the downstream ports:
• Primary Bus Number – All downstream port numbers are the Device Numbers
on the internal virtual PCI Bus (Bus Number register, offset [7:0])
• Secondary Bus Number – Identifies the port’s downstream link
(Bus Number register, offset [15:8])
• Subordinate Bus Number – Must be the last (largest) Bus Number in the downstream
hierarchy of each downstream port (Bus Number register, offset 18h[23:16])
• Set the Command register Bus Master Enable and Memory Access Enable bits
(offset 04h[2:1], respectively)
• Base and Limit registers – Combines the memory of all downstream devices into one
large space, with the total size given by Limit - Base, and the Start address given by Base
On the upstream port, the primary side is accessed by a Type 0 Configuration access. The downstream
ports are accessed with a Type 1 Configuration access on the primary side of the upstream port, with the
Bus Number of each transaction equal to the upstream port Secondary Bus Number (Virtual PCI Bus).
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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